The capacitor is a critical element in radiofrequency and microwave circuits for high frequency wireless applications.
A metal-insulator-metal (MIM) capacitor is commonly used in high performance applications in CMOS technology. Typically, the MIM capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both parallel plates are typically formed from Al or AlCu alloys that can be patterned and etched through the use of several photolithography/photomasking steps. The thin insulating dielectric layer is typically made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD). However, MIM capacitors are costly to manufacture and show decreased performance in advanced nodes, such as 7 nanometer (nm) and 10 nm nodes.
Each integrated circuit (IC) of a particular device can be made up of billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, located on one or more chips of semiconductor substrate material. The quality and viability of a product including an IC therein can be at least partially dependent on the techniques used for fabricating the IC and the structure of various components therein. Fabrication of an IC can include two phases: front-end-of-line processes (FEOL) and back-end-of-line processes (BEOL). FEOL generally includes fabrication processes performed on a wafer up to and including the formation of a first “metal layer,” i.e., a metal wire for connecting several semiconductor devices together. BEOL generally includes fabrication processes following the formation of the first metal layer, including the formation of all subsequent metal layers.
Vertical natural capacitors (VNCAP) with stacked via-comb structures have emerged as an attractive option due to their low cost, high density, and highly symmetric configurations. However, VNCAP production methods are not compatible with advanced nodes.
A method for fabricating an IC structure including a vertical natural capacitor (VNCAP) includes applying a patterned mask over an IC structure wherein the IC structure having a dielectric layer during BEOL fabrication processes. The patterned mask is used to form a trench between a first metal formation and a second metal formation in the dielectric layer. The first metal formation and second metal formations are spaced apart from each other. A dielectric material is deposited in the trench so that the first metal formation and the second metal formation define a VNCAP. The process described in this publication requires patterning after metallization of the IC structure and deposition of a dielectric material in trenches.